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<title>ADDPS—Add Packed Single-Precision Floating-Point Values </title></head>
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<h1>ADDPS—Add Packed Single-Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>0F 58 /r ADDPS xmm1, xmm2/m128</td>
<td>RM</td>
<td>V/V</td>
<td>SSE</td>
<td>Add packed single-precision floating-point values from xmm2/m128 to xmm1 and store result in xmm1.</td></tr>
<tr>
<td>VEX.NDS.128.0F.WIG 58 /r VADDPS xmm1,xmm2, xmm3/m128</td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Add packed single-precision floating-point values from xmm3/m128 to xmm2 and store result in xmm1.</td></tr>
<tr>
<td>VEX.NDS.256.0F.WIG 58 /r VADDPS ymm1, ymm2, ymm3/m256</td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Add packed single-precision floating-point values from ymm3/m256 to ymm2 and store result in ymm1.</td></tr>
<tr>
<td>EVEX.NDS.128.0F.W0 58 /r VADDPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Add packed single-precision floating-point values from xmm3/m128/m32bcst to xmm2 and store result in xmm1 with writemask k1.</td></tr>
<tr>
<td>EVEX.NDS.256.0F.W0 58 /r VADDPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Add packed single-precision floating-point values from ymm3/m256/m32bcst to ymm2 and store result in ymm1 with writemask k1.</td></tr>
<tr>
<td>EVEX.NDS.512.0F.W0 58 /r VADDPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst {er}</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Add packed single-precision floating-point values from zmm3/m512/m32bcst to zmm2 and store result in zmm1 with writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FV-RVM</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Add four, eight or sixteen packed single-precision floating-point values from the first source operand with the second source operand, and stores the packed single-precision floating-point results in the destination operand.</p>
<p>EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.</p>
<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are zeroed.</p>
<p>VEX.128 encoded version: the first source operand is a XMM register. The second source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are zeroed.</p>
<p>128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.</p>
<h2>Operation</h2>
<p><strong>VADDPS (EVEX encoded versions) when src2 operand is a register</strong></p>
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] (cid:197) SRC1[i+31:i] + SRC2[i+31:i]
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE
                                                         ; zeroing-masking
                         DEST[i+31:i] (cid:197) 0
              FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] (cid:197) 0</pre>
<p><strong>VADDPS (EVEX encoded versions) when src2 operand is a memory source</strong></p>
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197)j * 32
    IF k1[j] OR *no writemask*
         THEN
              IF (EVEX.b = 1)
                    THEN
                         DEST[i+31:i] (cid:197) SRC1[i+31:i] + SRC2[31:0]
                    ELSE
                         DEST[i+31:i] (cid:197) SRC1[i+31:i] + SRC2[i+31:i]
              FI;
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE
                                                         ; zeroing-masking
                         DEST[i+31:i] (cid:197) 0
              FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] (cid:197) 0</pre>
<p><strong>VADDPS (VEX.256 encoded version)</strong></p>
<pre>DEST[31:0] (cid:197) SRC1[31:0] + SRC2[31:0]
DEST[63:32] (cid:197) SRC1[63:32] + SRC2[63:32]
DEST[95:64] (cid:197) SRC1[95:64] + SRC2[95:64]
DEST[127:96] (cid:197) SRC1[127:96] + SRC2[127:96]
DEST[159:128] (cid:197) SRC1[159:128] + SRC2[159:128]
DEST[191:160](cid:197) SRC1[191:160] + SRC2[191:160]
DEST[223:192] (cid:197) SRC1[223:192] + SRC2[223:192]
DEST[255:224] (cid:197) SRC1[255:224] + SRC2[255:224].
DEST[MAX_VL-1:256] (cid:197) 0</pre>
<p><strong>VADDPS (VEX.128 encoded version)</strong></p>
<pre>DEST[31:0] (cid:197) SRC1[31:0] + SRC2[31:0]
DEST[63:32] (cid:197) SRC1[63:32] + SRC2[63:32]
DEST[95:64] (cid:197) SRC1[95:64] + SRC2[95:64]
DEST[127:96] (cid:197) SRC1[127:96] + SRC2[127:96]
DEST[MAX_VL-1:128] (cid:197) 0
ADDPS (128-bit Legacy SSE version)
DEST[31:0] (cid:197) SRC1[31:0] + SRC2[31:0]
DEST[63:32] (cid:197) SRC1[63:32] + SRC2[63:32]
DEST[95:64] (cid:197) SRC1[95:64] + SRC2[95:64]
DEST[127:96] (cid:197) SRC1[127:96] + SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>VADDPS __m512 _mm512_add_ps (__m512 a, __m512 b);</p>
<p>VADDPS __m512 _mm512_mask_add_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);</p>
<p>VADDPS __m512 _mm512_maskz_add_ps (__mmask16 k, __m512 a, __m512 b);</p>
<p>VADDPS __m256 _mm256_mask_add_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);</p>
<p>VADDPS __m256 _mm256_maskz_add_ps (__mmask8 k, __m256 a, __m256 b);</p>
<p>VADDPS __m128 _mm_mask_add_ps (__m128d s, __mmask8 k, __m128 a, __m128 b);</p>
<p>VADDPS __m128 _mm_maskz_add_ps (__mmask8 k, __m128 a, __m128 b);</p>
<p>VADDPS __m512 _mm512_add_round_ps (__m512 a, __m512 b, int);</p>
<p>VADDPS __m512 _mm512_mask_add_round_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int);</p>
<p>VADDPS __m512 _mm512_maskz_add_round_ps (__mmask16 k, __m512 a, __m512 b, int);</p>
<p>ADDPS __m256 _mm256_add_ps (__m256 a, __m256 b);</p>
<p>ADDPS __m128 _mm_add_ps (__m128 a, __m128 b);</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>Overflow, Underflow, Invalid, Precision, Denormal</p>
<h2>Other Exceptions</h2>
<table class="exception-table">
<tr>
<td>VEX-encoded instruction, see Exceptions Type 2.</td></tr>
<tr>
<td>EVEX-encoded instruction, see Exceptions Type E2.</td></tr></table></body></html>